A radiofrequency (RF) signal may be amplified by a monolithic Multiplying Digital to Analog Converter (MDAC) if a radiofrequency signal is input as a reference signal and a binary code (digital word) is utilized to control, or modulate, the amplitude of the RF output signal. Such an arrangement may be referred to as a Radio Frequency Digital to Analog Converter (RFDAC).
FIG. 1 shows a polar transmitter 100 including an RFDAC circuit 110, and a signal processor circuit 120. The RFDAC circuit 110 is controlled by a digital amplitude signal (am), and driven by a phase modulated RF carrier signal (ap) generated by the signal processor circuit 120. Particularly, an input IQ base band signal (a) is first applied to a digital signal processor 10 which converts the analog IQ base band signal to digital (through Analog to Digital Converter (ADC) 11), and also transforms the signal into amplitude (am) and phase (ap) components (through Rectangular to Polar Converter (RPC) 12). In particular, the ADC 11 digitizes the input analog signal (a), and the RPC 12 translates the digitized wave into polar coordinates. RPC 12 outputs a digitized wave in polar coordinates, which takes the form R, P(sin) and P(cos), for example. In this example, the R coordinate represents an amplitude characteristic (am) of the digitized input wave. The P(sin) and P(cos) coordinates represent a phase characteristic (ap) of the digitized input wave.
The amplitude (am) and phase (ap) characteristics are then transmitted through separate paths in the polar transmitter 100. The amplitude characteristic (am) of the digitized input wave, comprising a digital word (DW) quantized into, for example, bits B0 to BN, with a Most Significant Bit (“MSB”) to Least Significant Bit (“LSB”), is scaled and filtered, by a digital signal processor 13, to form shaped digital pulses which are supplied to the RFDAC circuit 110. The DW may be of varying lengths in various embodiments. In general, the longer the DW the greater the accuracy of reproduction of the input analog wave (a) at the output of the RFDAC circuit 110.
In the exemplary embodiment shown in FIG. 1, the digital amplitude signal (am) is transmitted as an N-bit (e.g., 7-bit) DW through the digital signal processor 13, which scales and filters the digital bits of the DW before providing the digital bits to the RFDAC circuit 110. Each bit of the N-bit DW corresponds to a separate component control line am1-N (e.g., am1-7) in the RFDAC circuit 110. Each of the component control lines am1-N are coupled to a separate control component 22 (e.g., switching transistors 22a-g), which feeds into another transistor 25 (e.g., 25a-g), which is turned ON or OFF depending on the particular bit value on the control component line. For example, if the DW corresponding to the digital amplitude signal (am) is “1110000,” the first three (3) transistors (e.g., 25a-c) will be biased ON, and the last four (4) transistors (e.g., 25d-g) will be biased OFF. In this manner, the amplification of the input analog signal (a) may be effectively controlled, as explained below.
The digital phase signal (ap) is modulated onto a wave by way of Digital to Analog Converter (DAC) 18 and synthesizer 20. The synthesizer 20 preferably comprises a Voltage-Controlled Oscillator (VCO) in the exemplary embodiment. The synthesizer 20 provides an output wave (apout), which includes the phase information from the input wave (a). This output wave (apout) has a constant envelope (i.e., it has no amplitude variations, yet it has phase characteristics of the original input wave). The output wave (apout) may be further amplified by amplifier 24 before being provided to the plurality of transistors 25a-g on respective phase signal lines ap1-7.
Regulation of the transistors 25a-g may be accomplished by providing the digital word (DW) to the control components (e.g., switching transistors 22a-g). Each of the control components 22a-g preferably comprises a transistor acting as a current source. The control components 22a-g are switched by bits of the DW generated from the digital amplitude signal (am). For example, if a bit (e.g., the bit on line am1) of the DW is a logic “1” (e.g., HIGH), the corresponding control component (e.g., 22a) is switched ON, and so current flows from that control component to respective transistor segment (e.g., 25a). Similarly, if the same bit (e.g., the bit on line am1) of the DW is a logic “0” (e.g., LOW), the corresponding control component (e.g., 22a) is switched OFF, and so current is prevented from flowing through that control component to respective transistor segment (e.g., 25a). The current from all transistor segments 25a-g is then combined at the respective transistor outputs 26a-g, and provided as an output signal (b) on output signal line 27. Thus, by controlling the value of the DW, the amplification of the digital phase signal (ap) may be accurately controlled using the digital amplitude signal (am), thereby allowing reproduction of an amplified version of the input analog signal (a) at the output of the RFDAC circuit 100.
FIG. 2 shows a conventional bias circuit 200 for biasing each of the transistor segments 25a-g of the RFDAC circuit shown in FIG. 1. The bias circuit 200 includes a first transistor 210 (Q2) with its base coupled to a reference voltage terminal Vref, a second transistor 220 (Q1) with its collector terminal also coupled to Vref, and a third transistor 230 (Q0) with its base coupled to an input radio frequency signal at RFin. In this schematic, the third transistor 230 (Q0) represents each transistor segment (e.g., transistors 25a-g) of the RFDAC (i.e., a separate bias circuit 200 would provide a bias signal to each of the transistors 25a-g of the RFDAC circuit 100).
The bias circuit 200 provides a current at its output which is a scaled copy of the input current (i). The scale factor is determined by the geometric relationship between the second transistor 220 (Q1) and output transistor 230 (Q0). The input current (i) is derived from a voltage source (VCon) driving an input resistor R1. When an RF carrier is input (at input terminal RFin) to the base terminal of the third transistor 230 (Q0) through a coupling capacitor CH, an amplified RF signal appears at the output (RFout) terminal of the bias circuit 200. The RF output signal is superimposed on a DC level determined by the input current (i) and the geometric scaling (i.e., geometry of transistors Q0, Q1). The output RF signal may be varied, or turned ON or OFF at will by varying the input voltage (VCon).
A requirement of the RFDAC architecture is that the turn-ON and turn-OFF of the RF output signal occur according to a Low Pass Filter (LPF) response. A LPF disposed at the output of the RFDAC is not preferred, as it would attenuate the average RF signal. Moreover, filtering the input to the RFDAC with an LPF is possible, but is complicated by the inherent non-linearity of the Bipolar Junction Transistors (BJTs), which comprise the transistors 25a-g of the RFDAC. The transfer function of the BJT (i.e., output current versus input voltage) is highly non-linear due to the exponential relationship between the input voltage and output current known as the ‘diode equation.’ Closed-loop techniques are highly effective for reducing non-linearity in circuits which are biased continuously in the ON-state, but in the transition regions from OFF-ON or ON-OFF, closed-loop dynamics can add new distortion effects due to slewing and phase margin variations.
Thus, there is presently a need for a system for effectively biasing the RFDAC such that it displays an LPF output response, but does not utilize a LPF coupled to the input or output thereof.